使用自動對準閘極技術以提升六十奈米砷化銦通道量子井場效電晶體的直流與高頻特性

Abstract

近年來，高速電子元件在高頻應用的發展十分迅速，目前已進入到毫米波甚至是次毫米波的領域裡，因此，對於元件規格的要求日趨嚴苛。由於三五族化合物半導體元件表現較矽半導體元件優異，所以三五族化合物半導體元件目前在高速及高頻應用上顯得極為重要。為了提升三五族半導體元件在高頻之表現，有許多元件及材料的改良方式被提出，例如：異質接面結構及次奈米Ｔ型金屬閘極。在本論文，我們將探討藉由源極與集極間距之微縮技術來進一步增進元件特性。 在本實驗中，將使用改良型自動對準閘極技術來縮減源極與集極間之間距。實驗之磊晶試片是由分子束磊晶系統所成長，其結構具備有高電子遷移率複合通道層InAs/In0.53Ga0.47As以及高濃度參雜(2x1019)的Cap層。本論文之自動對準閘極技術前端製程與傳統的量子井場效電晶體製程相同，包括：定義元件操作之主動區、歐姆接觸的形成以及Ｔ型金屬閘極的定義；經過閘極金屬蒸鍍過後，便開始進行本論文所設計的自動對準閘極技術。首先，先沉積以二氧化矽所構成的保護層來保護六十奈米的Ｔ型金屬閘極，其次，使用氫氟酸移除主動區域之二氧化矽保護層並隨後立即蒸鍍上歐姆接觸所使用之金屬，最後再沉積氮化矽做為元件的保護層並進行接觸窗部位的開啟。 比較使用與未使用自動對準閘極技術的元件，可以使用自動對準閘極技術之元件在直流的特性上有很顯著的提升，其集極飽和電流密度從原先的391 mA/mm提升到517 mA/mm，同時，轉移電導也使用過自動對準閘極技術的製程之後由946 mS/mm上升至1348 mS/mm；此外，與放大特性息息相關的電流增益截止頻率也由187 GHz提升至205 GHz。本實驗之自動對準閘極也改進了元件的邏輯應用特性，其汲極引致能障下降降為75.6 mV/V、次臨界擺幅降為101.4 mV/dec而開關電流比(ION/IOFF ratio)則為3300。這些成果顯示此種改良型的自動對準閘極技術能夠有效提升三五族量子井場效電晶體在高速、高頻應用之功能，並同時具備元件低能量消耗的效果。

In general, III-V compound semiconductors have significantly higher intrinsic mobility than silicon and substrates are semi-insulating. These material properties combine with band gap engineering, epitaxial layer growth technique and process technologies result in devices with excellent performance at high frequencies. The applications for these devices include broadband optical fiber communication, wireless communication at millimeter wave and sub-millimeter wave range. Recently, InGaAs Quantum Well Field Effect Transistor (QWFET) also shows great promise for future high-speed and ultra-low power logic application due to its high speed and low voltage operation capability. In this experiment, the epitaxial layers of the InAs/In0.53Ga0.47As-channel QWFET with highly doped (2 x 1019) cap layer were grown on InP substrate by molecular beam epitaxy (MBE) for high speed device application. The devices were fabricated with the self-aligned gate technology. The device fabrication was started with a conventional QWFET process: mesa isolation, ohmic contact formation and T-shape gate definition. After the gate metals were deposited, the self-aligned gate process was executed. First, the SiO2 layer was deposited as a hard mask by PECVD to protect the 60 nm T-shape gate. Then, the SiO2 within the mesa region was removed by HF. Then an extra thin ohmic metal (Au) layer was deposited by E-gun evaporator. Finally, the device was passivated by SiNx and the contact via was etched with RIE. Comparison of the devices with/without the SAG process shows that there is obtains improvement of the saturation drain current density from 391 mA/mm to 517 mA/mm after using the SAG process. The transconductance also enhanced from 946 mS/mm to 1348 mS/mm and the current gain cutoff frequency changed from 187 GHz to 205 GHz. Furthermore, the device with SAG process had great performance for logic application: ION/IOFF ratio = 3.3 x 103, DIBL = 75.6 mV/V and S.S. = 101.4 mV/dec. These results show that the ameliorative self-aligned gate technology can effectively enhance the III-V QWFET device performance for high frequency, high-speed and low-power consumption applications.