高速與低偏壓砷化銦通道量子井場效電晶體在高頻及邏輯應用之研究

Abstract

近年來無線電頻率特別是毫米波、次毫米波頻段的應用，已經對人類的日常生活產生重大的影響。其所應用的範圍包括有行動通訊、軍事國防、交通指引、雷達系統等；除此之外，其他一些仍在發展中的應用例如家園防護系統、醫藥分析、高解析度影像感測系統等，其研究也如火如荼的進行中。而尋找在高頻頻段下仍擁有極高增益、低雜訊的元件是這類應用的重要關鍵。由於三五族砷化銦鎵材料的高電子遷移率以及量子井場效電晶體優異的能帶設計，因此三五族砷化銦鎵通道量子井場效電晶體在這方面的應用展現極大潛力。 在此研究中，成功的製作了四十奈米閘極線寬的砷化銦通道量子井場效電晶體，並且透過先進的二次閘極蝕刻以及白金閘極掘入技術，使元件展現優異的高頻特性。此研究比較了在低操作偏壓下(VDS=0.5V)使用此先進製程技術的砷化銦量子井場效電晶體與未使用此製程的元件，發現透過此兩先進製程步驟，元件展現較佳飽和電流、較低輸出電導、較小負截止電壓，以及較高的電流增益截止頻率和功率增益截止頻率(可分別達到440GHz以及190GHz)。除此之外，針對此元件進行雜訊品質的量測，發現即使在高頻64GHz下，其雜訊指標仍低於2.5分貝。由這些特性可以得知，四十奈米的砷化銦量子井場效電晶體是適用於高增益、低雜訊以及低操作偏壓的高頻元件應用。 然而，由於砷化銦材料的窄能隙特性，衝擊離子化效應的現象很容易發生。在這份研究中，透過實驗數據的分析，具體地證實四十奈米砷化銦量子井場效電晶體的衝擊離子化效應，其中包括隨著施加偏壓劇烈上升的汲極電流以及在VDS>1.0V時所觀察到的鐘型閘極漏電曲線，此外，還有包括在VDS=1.0V時急遽上升的雜訊指標以及VDS=1.0V時下降的電流增益等，都是衝擊離子化效應發生的明顯證據。雖然衝擊離子化現象破壞了元件的特性，然而只要選擇適當的操作偏壓，仍可得到相當優異的元件特色；例如當VDS在相當低的0.5V時，其轉移電導即可達到1500 mS/mm，還有在高頻64GHz下，其雜訊指標仍低於3分貝，此外，在此研究中還發現，當施加的偏壓在衝擊離子化即將發生的電壓前，可得到663GHz極高的電流增益截止頻率。由以上分析可知，只要選擇適當的操作偏壓，四十奈米砷化銦量子井場效電晶體是相當適合於毫米波以及次毫米波元件應用的。 這份論文的最後，另外針對四十奈米砷化銦量子井場效電晶體於未來高速邏輯電晶體運用做評估，發現在低偏壓下(VDS=0.5V)元件展現相當優異的邏輯特性，包括其汲極引致能障下降是相當低的50mV/V，而次臨界擺幅也是相當低的89mV/decade，此外，此元件的閘極延遲時間低於1.0psec，而與Si NMOSFET做比較，其閘極延遲時間也是較低的。而這些研究結果可以證實四十奈米砷化銦量子井場效電晶體是極有潛力作為未來後矽半導體世代高速邏輯電晶體的使用。

Recently, wireless communication applications at millimeter wave band and sub-millimeter wave bands have gained a lot of momentum. The applications include wireless systems, cellular backbone, national weaponry, traffic guidance, radar systems, etc. Besides, emerging millimeter wave applications such as homeland security, medical diagnosis, and high-resolution image sensor are also in development rapidly. Therefore, development of the devices possessing both high frequency features and low noise characteristics is becoming urgent. High indium content InGaAs-based QWFETs are particularly promising because the excellent electrical properties of InxGa1-xAs material and the superior band-gap design of QWFET. In this study, the 40 nm InAs QWFETs processed with advanced two-step recess and Pt gate sinking technologies for RF applications are fabricated. The developed 40 nm InAs QWFETs with these advanced processes exhibit better performance than the conventional InAs QWFETs at low applied voltage such as better current saturation, lower output conductance (go), smaller negative threshold-voltage (VT), higher current-gain cut-off frequency (fT) of 440 GHz and higher maximum oscillation frequency (fmax) of 190 GHz. Besides, the 40 nm InAs QWFETs with advanced processes also exhibit the minimum noise figure of lower than 2.5 dB up to 64 GHz when biased at VDS of 0.5 V. The excellent electronic performances indicate the developed 40 nm InAs QWFETs are suitable for high-gain, low noise and low voltage applications. However, because of the narrow energy band-gap of InAs channel material, the impact ionization occurred easily. In this study, the investigation of impact ionization phenomena in 40 nm InAs QWFETs is presented. The evidences of the occurrence of impact ionization in InAs QWFETs include the high output conductance with the increase of VDS, a hump in the curve of gate leakage current at VDS higher than 1.0 V, the drastically increase of minimum noise figure at VDS of 1.0 V, and the reduction of fT at VDS of 1.0 V. Although the impact ionization degrades the performance of the devices, the excellent characteristics can still be achieved with optimal bias selection. The devices show transconductance over 1500 mS/mm at VDS of 0.5 V. Besides, low noise figure of less than 3 dB with an associated gain of 7 dB up to 64 GHz at VDS of 0.8 V are observed. And the extremely high fT of 663 GHz can be obtained if the devices are biased near the occurrence of impact ionization. Therefore, with optimal bias conditions, InAs QWFETs can achieve tremendous high performance for high-speed sub-millimeter wave applications. In addition to high frequency RF applications, the evaluations of 40 nm InAs QWFETs for high-speed logic applications have also been demonstrated in this study. The devices show outstanding logic performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 50 mV/V, subthreshold swing (S) is 89 mV/decade, and intrinsic gate delay (CV/ION) is less than 1.0 psec. When comparing to the mature Si technology, the InAs QWFETs exhibit smaller gate delay time. Besides, InAs QWFETs show much higher ION/IOFF performance than the most advanced InSb QWFETs. These results demonstrate that the 40 nm InAs QWFETs have great potential for future high-speed and low-voltage logic applications.