標題: 具生物反餽機制之智慧型長時睡眠監測系統---子計畫三:應用於長時生理訊號儲存系統之無失真錯誤更正機制(I)
Design and Implementation of Lossless Error Correction Codes for Long-Time Physiological Signal Storage Systems(I)
作者: 張錫嘉
Chang Hsie-Chia
國立交通大學電子工程學系及電子研究所
關鍵字: 無失真壓縮技術;離散餘弦轉換;快閃記憶體;錯誤更正機制;Reed-Solomon Codes;BCH Codes;LDPC Codes;Lossless Compression;Discrete Cosine Transform;Discrete Wavelet Transform;FlashMemory;Error Correction Codes;Reed-Solomon Codes;BCH Codes;LDPC Codes
公開日期: 2009
摘要: 長時生理訊號的量測,往往會產生相當可觀的資料量。以心電圖的量測為例,倘若使用最低的取樣率、精確度並且不考慮任何附加資訊,單一感測器每分鐘將產生7.5K Bytes,也就是每八個小時就會有3.6M Bytes的數據資料。在睡眠監測系統的應用上,我們推估需要數十甚至上百個感測器來得到腦電波、心電圖、口鼻氣流、血氧濃度、甚至睡姿等相關資訊,所產生龐大的資料量除了要有大容量的多通道儲存裝置,也需要針對各種生理訊號的特性開發無失真壓縮技術。據此,本計畫擬藉由離散餘弦轉換(Discrete Cosine Transform)發展二維以及可調式的訊號壓縮技術,期許能同時降低記憶體需要量以及運算上的複雜度。 此外,為因應資料儲存在大容量、小體積、低功耗等相關需求,本計畫擬以快閃記憶體作為儲存媒介。然而隨著製程的演進,每個記憶體單元已經由傳統儲存1位元資料的SLC(single level cell)演進到能夠儲存2、3位元的MLC(multiple level cell),這意味著表示我們無法避免的良率與穩定度下降的問題,也代表錯誤更正碼在快閃記憶體的使用上將越來越重要。據此,本計畫將針對MLC的特性,導入非對稱式channel model,結合目前通訊系統廣泛使用的RS、BCH、或者LDPC codes來作為下世代快閃記憶體的錯誤更正機制。
Huge amount of data is usually required for a long-time physiological signals measurement. For example, with the lowest sampling rate and without any additional information, 7.5K-Bytes data will be generated by an electrocardiograph sensor per second, indicating 3.6M-Bytes statistical data will be generated per eight hours. In the application of sleep-monitoring systems, it is estimated that we need more than hundreds of sensors to get electroencephalogram (EEG), electrocardiogram (ECG), oronasal airflow, SpO2 and the sleeping positions information. Hence, we develop the multi-dimension and multi-rate lossless compressing techniques from DCT (Discrete Cosine Transform) and DWT (Discrete Wavelet Transform) in this project. In addition, we plan to use flash memories as storage elements for the requirement of large capacity, small size and low power issues. However, each memory element has been improved from SLC (single level cell), which could store 1 bit data, to MLC (multiple level cell), which could store 2~3 bits data. It means that we have to face the problems of decreasing yield and stability. In this project, we will use the MLC characteristic to develop the asymmetric channel model, which will be combined with RS、BCH or LDPC codes to provide better error correction mechanism for the next generation flash memories.
官方說明文件#: NSC98-2220-E009-056
URI: http://hdl.handle.net/11536/101554
https://www.grb.gov.tw/search/planDetail?id=1904263&docId=315564
顯示於類別:研究計畫