以I-line 雙重曝影技術研製次100奈米線寬穿隧式場效電晶體

Abstract

遵循摩爾定律發展的積體電路產業使晶片的總耗電量也呈驚人的成長。根據一項統計數據，2007年美國總用電量的7 ％左右是由積體電路晶片所貢獻。在今後如果放任積體電路產業的成長卻沒有提出減少功率消耗的解決方案的話，將會造成嚴重能源短缺的後果，微電子產業對“綠色”技術需求的迫切性不言可喻。為了實現在室溫下讓次臨界擺幅小於理想值60mV/dec的目的，新穎元件穿隧式場效應電晶體（TFET）概念已被提出，並被視為是最具潛力的一項技術。對於關閉狀態的n型通道穿隧式場效電晶體，逆偏的pin二極體可以提供低的關閉電流。另一方面，當閘極電壓高於臨界電壓時，源極區域的價電帶將會對齊，甚至高於通道區域的導電帶，使得穿隧寬度明顯減小，而產生元件的開啟態驅動電流並使次臨界擺幅在室溫下小於理想值60mV/dec。本計劃首先將發展I-line雙重曝影技術，用以形成線寬低於100奈米的元件通道長度，並搭配不對稱的p型與n型源極/汲極設計與製作，研製與分析奈米級穿隧式場效應電晶體。

The total power consumed by the IC chips increases at a very high rate with the aggressive development of IC industry which follows the well-known Moore’s law. In 2007, around 7% of US electricity use may be attributed to IC use. It will become a catastrophic scenario if there are 10 times more ICs in the future without power dissipation scaling solution. Development of a “green” device technology which can dramatically cut down the power consumption during operation is thus an urgent need. Among several candidates, tunneling field-effective transistor (TFET) is widely believed the one most promising to succeed the modern CMOS technology. For an n-channel TFET, in the off state, the energy barrier between the source and channel region is wide enough to prevent tunneling from happening and the reverse-biased P-I-N diode renders a low off current. While in the on state when gate voltage is larger than the threshold voltage, the valence band of the source region is aligned with or even higher than the conduction band of the channel region so that the tunneling width is significantly reduced giving rise to device current. Subthreshold swing of sub-60 mV/dec is thus achievable as the device structure is cleverly designed. In this project, a simple I-line double-patterning technique is proposed and developed to generate sub-100 nm patterns and to aid the fabrication of TFET devices with appropriate design and implementation of asymmetrical source and drain structure.