前瞻矽奈米元件變異性及傳輸特性綜合研究(I)

Abstract

在此研究計畫中，我們將對以矽為基底的前瞻奈米元件，針對其變異性及載 子傳輸特性，進行綜合研究。在工作項目一中，我們將分別對超薄基體(UTB)， 多閘極(multi-gate)以及gate-all-around 奈米線金氧半場效電晶體，建立一套 包含Poisson 及Schrodinger 方程式之解的理論架構。利用這一套可考慮量子效 應的解析解模型，我們將研究這三種元件結構並搭配不同的通道材料，其對製程 變異的敏感度。我們的元件模型也將有助於未來奈米級元件的設計。在工作項目 二中，我們將廣泛地研究先進CMOS 場效電晶體的隨機不匹配特性(random mismatch)。這項研究不僅對使用先進CMOS 元件的電路設計很重要，也有助於對 奈米元件的本質參數變異(intrinsic parameter fluctuation)的根本了解。在 工作項目三中，我們將對奈米級應變矽元件的戴子傳輸特性進行研究。這項研究 將有助於了解極微縮應變矽元件的戴子傳輸機制，也對未來提昇戴子遷移率的元 件設計有所幫助。

In this project we conduct a comprehensive study of variability and carrier transport for advanced silicon-based nanodevices. In task I, we will establish a theoretical framework that includes the solutions of Poisson and Schrödinger equations for UTB, multi-gate and GAA nanowire MOSFETs. Using the analytical models, we will assess the sensitivity of these structures with various channel materials to process variations considering quantum-mechanical effects. Our physical models will be instrumental for future nanoscale device designs. In task II, we will conduct a comprehensive study of random mismatch for advanced CMOS devices. This study is important not only for circuit designs using advanced CMOS devices, but also for the fundamental understanding of intrinsic parameter fluctuations in nanodevices. In task III, we will conduct a comprehensive study of carrier transport for nanoscale strained MOSFETs. Our investigation will contribute to unveiling several puzzles regarding carrier transport in ultra-scaled strained devices, as well as providing insights for future mobility scaling.