針對3D整合之電子設計自動化技術開發---子計畫一：三維度積體電路的隨機電熱模擬及其對功率最佳化的應用(I)

Abstract

三維度積體電路已被視為有效克服二維度積體電路在導線連接瓶頸的架構。然而，較高的溫度 對三維度積體電路成了另一個嚴峻的挑戰。因為溫度會影響晶片電路的效能，所以必須降低電路上 的功率散逸。同時，由於物理參數的波動會嚴重地影響電路效能，因而製程變異在奈米積體電路設 計中亦被視為一個很重要的課題。本分項計劃將同時考慮此兩項議題於三維度積體電路。 此分項計畫的主要目的是研究和發展對於三維度積體電路隨機電熱模擬的技術和方法，並提出 三維度積體電路的功率降低技術。在計畫的初始階段，將探討三維度積體電路的實體特性如製造程 序過程、穿透矽基體導線的電器特性和三維度積體電路元件的製程變異影響。接著，此分項計畫將 開發隨機電熱特性模擬器以有效率且準確的預測三維度積體電路的統計型溫度分布。最後，並結合 多重電壓設計技術發展出考慮三維度積體電路中時序受製程變異和熱因素影響的功率最佳化技 術。

The three-dimensional integrated circuit (3-D IC) has been viewed as an effective methodology to overcome the bottleneck caused by the interconnect in the two-dimensional integrated circuit (2-D IC). However, the higher temperature becomes a big challenge for 3-D ICs. On-chip temperature can significantly affect the circuit performance so it is necessary to reduce the power dissipation in the circuit. Meanwhile, the process variations are regarded as important issues for the nanometer IC design because the fluctuation of physical parameters can seriously impact the performance of circuit. This subproject is going to investigate these two issues for the 3-D IC design. The goals of this subproject are to study the techniques and develop the methods of stochastic electro-thermal analysis for 3-D ICs, and propose statistical power reduction techniques for 3-D ICs. In the beginning, the physical properties of 3-D ICs such as manufacturing process, electro-properties of through silicon vias and process variation impacts of devices will be studied. Then, stochastic electro-thermal simulators will be developed to efficiently and accurately predict the statistical temperature distribution of 3-D ICs. Finally, we will develop a multiple supply voltage design technique with considering the process variations and thermal effects on circuit timing to optimize the power consumption of 3-D ICs.