次50奈米二位元儲存氮化矽快閃式記憶體元件之結構、電荷傳輸與可靠性研究

Abstract

快閃式記憶體技術已快速邁入100Gb 儲存世代，傳統之浮動閘極儲存架構已無法 繼續縮小，代之而起的是利用氮化矽內trap 儲存電子之元件結構。針對目前之二位元 氮化矽儲存元件，當元件尺寸小於50 奈米時，電子傳輸物理與可靠性機制均將發生 重大改變，現有之元件結構、儲存介質特性、操作方法是否適合，將面臨重大挑戰。 本計劃將針對次50 奈米世代，利用trap 儲存之二位元元件結構、儲存材料、操作方 法、電子傳輸與可靠性物理進行為期三年具前瞻性與深度之研究。在元件結構方面， 吾人將探討侷限性儲存（localized storage）之平面結構（例如Spacer SONOS），並進 一步研究雙閘極垂直式儲存元件（例如FinFET SONOS），在儲存材料方面，吾人首 要目標在於建立儲存介質內trap 特性之量測方法與指標，並比較不同材料（例如SiN， AlN 或HfO）之trap 行為（例如density、trap energy）在傳輸物理與可靠性量測方面。 吾人將利用所建立之單電子量測系統，測量單一電子進出儲存介質之性質，並研究影 響元件電流之所有可能機制。在理論模擬方面，吾人將利用蒙地卡羅程式，計算單一 電子進出儲存介質對於通道內電子傳輸行為之影響，並計算二位元操作下儲存電子之 空間分佈。 本計劃之目的在於探討二位元利用trap 儲存之快閃式元件物理限制，scaling 時可 能產生之新的failure 機制，與評估新元件結構及材料與可能之突破方向。

As the flash memory technology is moving rapidly into 100Gb regime, conventional floating gate flash memory suffers from serious coupling interference between cells, thus limiting its further scaling above 50nm technology node. Nitride storage flash (such as SONOS) now has been considered to be the most promising candidate in the 100Gb era owing to its non-conducting storage media. For the dual bit storage SONOS cells, drastic changes are expected with respect to charge transport and reliability mechanisms when cell length is scaled below 50nm. New cell structures, storage materials and innovations in cell operation are required to meet the sub-50nm cell specifications. In this three-year proposal, we will initiate research towards the understanding of charge transport physics (such as single charge phenomena) and new reliability and failure mechanisms in sub-50nm SONOS cells. In this project, we will explore the constraints of two-bit operation in various SONOS structures from localized storage cells (spacer SONOS) to vertical storage cells (FinFET). For trapping material, we will develop a method to characterize trap energy distribution and trap density. Therefore, we are able to evaluate trapped charge retention capability in different storage materials (for examples, SiN, AlN, HfO..). With respect to charge transport and reliability, we will use a newly developed fast transient measurement setup to monitor individual charge retention loss and read current fluctuation arising from single charge trapping/detrapping. From the single charge phenomena measurement, dominant reliability mechanisms and various transport effects (for example, random telegraph noise and trapped charge incurred mobility degradation) can be determined. In theoretical part, since conventional drift-diffusion concept is no longer appropriate for sub-50nm devices, we will use Monte Carlo simulation to calculate programmed charge spatial distribution and thus to evaluate the substrate engineering effect on the 2nd bit effect. The current fluctuation due to trapped charge induced Columbic scattering will also be analyzed by the Monte Carlo method. In short, the purpose of this project is multi-fold; First, we will identify possible physical limits in the present 2-bit storage SONOS scaling. We will also develop a direct trap monitor for new storage material evaluation. Finally, we will investigate new SONOS structures and operation methods for the coming 100Gb era.