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dc.contributor.authorWu, Chung-Yuen_US
dc.contributor.authorChen, Po-Hungen_US
dc.date.accessioned2014-12-08T15:13:14Z-
dc.date.available2014-12-08T15:13:14Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1377-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/10222-
dc.description.abstractIn this paper, a low power V-band low-noise amplifier (LNA) using standard 0.13-um CMOS technology is proposed and analyzed. In the proposed LNA, three-stage common-source topology is used instead of cascode configuration to improve the noise performance. The measured LNA gain is 10.9 dB and the simulated noise figure of the proposed LNA is 5.1 dB at 67.8 GHz. Furthermore, the input and output return losses are lower than -12 dB at center frequency. Moreover, the 3-dB bandwidth covers from 65 GHz to 72 GHz which is suitable for wideband applications. Finally, the proposed LNA consumes only 5.4 mW from a 0.8-V power supply.en_US
dc.language.isoen_USen_US
dc.titleLow power V-band low noise amplifier using 0.13-mu m CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4en_US
dc.citation.spage1328en_US
dc.citation.epage1331en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000255014801152-
Appears in Collections:Conferences Paper