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dc.contributor.authorShi, WPen_US
dc.contributor.authorChang, MFen_US
dc.contributor.authorFuchs, WKen_US
dc.date.accessioned2014-12-08T15:02:20Z-
dc.date.available2014-12-08T15:02:20Z-
dc.date.issued1996-10-01en_US
dc.identifier.issn0018-9340en_US
dc.identifier.urihttp://dx.doi.org/10.1109/12.543713en_US
dc.identifier.urihttp://hdl.handle.net/11536/1023-
dc.description.abstractFor a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the ''shifting'' reconfiguration as weighted chains in a partial ordered set, we prove when n = Theta(m), the harvest rate is between 34% and 72%.en_US
dc.language.isoen_USen_US
dc.subjectharvest rateen_US
dc.subjectyielden_US
dc.subjectreconfigurable arraysen_US
dc.subjectdefect toleranceen_US
dc.subjectpipelinesen_US
dc.subjectrandom graphsen_US
dc.subjectpercolationen_US
dc.titleHarvest rate of reconfigurable pipelinesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/12.543713en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTERSen_US
dc.citation.volume45en_US
dc.citation.issue10en_US
dc.citation.spage1200en_US
dc.citation.epage1203en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1996VT47500010-
dc.citation.woscount1-
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