完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shi, WP | en_US |
dc.contributor.author | Chang, MF | en_US |
dc.contributor.author | Fuchs, WK | en_US |
dc.date.accessioned | 2014-12-08T15:02:20Z | - |
dc.date.available | 2014-12-08T15:02:20Z | - |
dc.date.issued | 1996-10-01 | en_US |
dc.identifier.issn | 0018-9340 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/12.543713 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/1023 | - |
dc.description.abstract | For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the ''shifting'' reconfiguration as weighted chains in a partial ordered set, we prove when n = Theta(m), the harvest rate is between 34% and 72%. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | harvest rate | en_US |
dc.subject | yield | en_US |
dc.subject | reconfigurable arrays | en_US |
dc.subject | defect tolerance | en_US |
dc.subject | pipelines | en_US |
dc.subject | random graphs | en_US |
dc.subject | percolation | en_US |
dc.title | Harvest rate of reconfigurable pipelines | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/12.543713 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTERS | en_US |
dc.citation.volume | 45 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 1200 | en_US |
dc.citation.epage | 1203 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:A1996VT47500010 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |