電子式硬碟之測試與重組

Abstract

全晶圓積體是一種新的電路包裝技術,電子式硬碟是全晶圓積體設計的一 種應用,一個電子式硬碟中包含了數百個記憶體單元, 為了要使電子式硬 碟能順利的工作,必須先把電子式硬碟中的記憶體單元,連成一個線性陣 列,由於在電子式硬碟中的任何一個組件 , 都可能因電路的瑕疵而無法正 確的工作因此,把記憶體連成線性陣列的工作 , 將會是一個 "非多項式時 間能完成" (NP-Complete) 的演算法, 現今針對"記憶體連結成線性陣 列" 問題所發展的演算法多為 "啟發式"演算法 (heuristic algorithm), 針對連結問題,我們先提出了一個扭曲迴圈式設計 (twisted loop-based design),這項設計比迴圈式設計(loop-based design)更為廣泛,並且針 對 "扭曲迴圈式設計"我們也提出了一個圖形模型,"迴圈式設計"同樣也可 以用這個圖形模型來表示, 基於這個圖形模型我們發展了一個"啟發式"重 組演算法,這個演算法提供的回收率比 Chang & Fuchs 的還高,我們也分 析了連結路徑上"功能錯誤 "(functional fault) 並將這些功能錯誤歸類 成三種模式,根據這項結果我們提出了一套包含了 "自我測試" 與 "交互 測試" 的測試程序,並且設計了一個利用此項測試程序結果的"連結路徑初 始設定"initialization)的程序 Wafer Scale Integration ( WSI ) is a new packaging technology. Solid State Disk ( SSD ) is an application of Wafer Scale Integration. A SSD contains hundreds of memory cells. To make SSD work, memory cells on SSD have to be linked into a linear array. Any elements of SSD may fail to work. Thus, linking the good memory cells into a linear array will be an NP-complete problem. Most contemporary linking algorithms developed are heuristic algorithms. In this thesis, we propose a twisted loop- based interconnection design which is more general than the loop- based design. A graph model which is used to represent twisted loop-based design is proposed. This graph model can also represent the loop-based design. Based on this graph model, we develop a heuristic reconfiguration algorithm which provides a better harvest rate than Chang and Fuchs. We also analysis the interconnection path's functional faults. The faults are classificated into three kinds. Based on this classification, a diagnosis process which contains self-test and mutual-test schemes are proposed. A initialization procedure using the diagnosis results is presented, too.