電子式硬碟的製作

Abstract

雖然WSI的可行性已被爭議了很久，但WSI仍有許多優點，例如低功率消耗 ，體積小，較低的成本等等。在我們的計畫中，我們實際應用WSI的技術 去設計一個全晶圓電子式硬碟(SSD)，全晶圓電子式硬碟並沒有移動的機 械元件，這是它和傳統磁碟不一樣的地方，它能提供較低存取廷遲，較寬 的資料頻寬及可靠的資料存取。我們希望能以全晶圓電子式硬碟 (SSD)取 代速度慢，體積大，且功率消耗大的傳統式碟。為了避開晶圓中壞掉的單 元，我們採用迴圈式容錯的連結方式去連結單元。我們在每一個單位的四 週放四個多工器，用來作單元間的聯結用。每一個單位包含一個控制單元 及一個記憶體單元，除了要模擬磁碟的區塊讀寫動作，控制單元還有一組 特殊的內建測試指令。這些內建測試指令能用來合成大多數現在記憶體測 試程序。因為這些單元是被連結成一個線性陣列，記憶體測試程序能以管 線式的方式應用在每一個單元，因此全晶圓電子式硬碟對一整個晶圓的測 試時間約等於對一個個單元的測試時間。我們是以"Divide and conquer" 的方式來設計全晶圓電子式硬碟。首先這系統功能是由Verilog來描述， 並利用Verilog-XL模擬器 (simulator)來測試系統描述是否正確。再利用 Synopsys邏輯合成工具來合成"Verilog描述"而轉成邏輯閘層次電路。我 們再以Verilog模擬器來測試邏輯閘層次電路之功能與時序是否正確。最 後我們利用Cadence Opus將邏輯閘層次之電路設計，製成實體IC之排版( layout)。我們使用的是電通所提供TSMC .8um的cell library與SRAM元件 。 Wafer Scale Integration (WSI) has many potential advantages such as low power consumption, small volume, low system cost, etc. Nevertheless its feasibility has been disputed for a long time. In this project, we design an electronic Solid-State Disk (SSD) which is a practical application of WSI. Since a SSD, unlike conventional magnetic disks has no moving mechanical parts in it, it can provide low data access latency, high data transfer bandwidth, and reliable data access. In order to bypass faulty memory cells on the wafer, we adopt a loop-based defect-tolerant interconnection to link the memory cells. Each cell consists of a control unit and a memory unit. In addition to emulating sector read/write operations of a magnetic disk, the control unit has a set of verification functions built-in; the verification functions are specially designed, so that most existing memory testing procedures can be composed by these verification functions. Since the cells are linked into a linear array, testing of a SSD can be done in a pipelining fashion by issuing verification commands to all cells . Thus, the testing time of a SSD is reduced to about the same order as the testing of a memory unit in the SSD. We also design the circuit using a divide and conquer approach. First, Verilog is used to describe the system functions. The functions are then verified by Verilog simulator . Synopsys logic synthesis tools are used to synthesize our design into gate-level circuits. Verilog-XL simulator is used to verify the functional and timing correctness of gate-level circuits. Cadence OPUS is used to implement the physical layout of our design.