全晶圓容錯記憶體系統設計

Abstract

全晶圓積體電路的可行性已經經過了許多年的研究和發展，它有許多的優 點，如低功率消耗,體積小,低系統發費等等。我們利用全晶圓的方式來設 計一個電子式硬碟系統，由於電子式硬碟不像一般的磁碟機具有機械部份 ，所以它能提供較高的資料頻寬和可靠的資料存取，而成為主記憶體和硬 碟之間的一個中介點。 為了要避開晶圓中有瑕疵的記憶體單元，我們使 用迴圈容錯的連結方式來連接記憶體單元，為了要降低晶圓中面積的負 擔 (area overhaed) 和維持可靠度， 我們採用串列的方式來傳送資料。 同時我們也提出一個平行的測試方法，它是利用內建的驗證電路以一種管 狀的方式來測試所有的記憶體單元。我們使用從上而下 (top-down) 的方 式來設計我們的電路，首先我們用 VHDL 來描述此電路的功能，並且以 VHDL模擬器來驗證我們的描述，然後用Synopsys的合成工具來合成我們的 設計，使之成為gate-level的電路。 Wafer Scale Integration (WSI) has many potential advantages such as low power consumption, small volume, low system cost, etc . Nevertheless its feasibility has been investigated for a long time. In this thesis, we design an electronic Solid- State Disk ( SSD) which is a practical application of WSI. Since SSD unlike magnetic disk has no moving mechanical parts in it,it can provide high data bandwidth and reliable data access. SSD can fill the latency gap in memory hierarchy between high speed, high priced main memory and low speed, low priced hard disk. In order to bypass faulty memory cells on the wafer, we adapt a loop-based defect-tolerant interconnection to link memory cells. The interconnection is bit-serial in order to reduce area overhead and to maintain reliability. We also propose a parallel testing method which utilizes built-in verification circuit to test all the cells in a pipelined fashion. We design the circuit in a top-down approach. First, we use VHDL ( VHSIC hardware description language ) to describe its functions, and verify the description by VHDL simulator. Then Synopsys logic synthesis tools are used to synthesize our design into gate-level circuits.