A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes

Abstract

A new architecture of charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes is proposed, which is composed of two identical pumping branches and four-phase clock signals. The four-phase clock signals are designed to have no undesirable return-back leakage path during clock transition and to control the charge transfer MOSFET switches in the proposed circuit to be turned on and off completely. Therefore, its pumping efficiency is higher than that of the conventional one. Because the gate-to-source and gate-to-drain voltages of all devices in the new proposed charge pump circuit do not exceed the normal power supply voltage (VDD), the new proposed charge pump circuit is suitable for applications in low-voltage CMOS processes.