标题: 使用60GHz之室内十亿级位元传输率之无线基频传收机---总计画(I)
Core SoC Technologies for Indoor 60GHz Multi-Gbps Wireless Baseband Transceiver(I)
作者: 周世杰
JOU SHYH-JYE
国立交通大学电子工程学系及电子研究所
公开日期: 2008
摘要: 本计画目标在于开发前瞻之室内亿级位元传输率基频传收机之SOC 设计技术及相
关之关键性智产平台与设计法则。计画拟以在制定中适用于室内亿级位元传输率之无线
基频传收机作为技术开发之载具,并将设计延伸至无线高解析多媒体影音介面(Wireless
High Definition Multimedia Interface, WirelessHDMI)应用,以设计出相关标准之室内亿级
位元传输率之无线基频传收机之关键IP 及系统晶片。计画目标是发展下列关键技术包
括:
1. 室内亿级位元传输率之无线基频传收机及延伸至 WirelessHDMI 基频传收机之
系统设计及效能评估。
2. 室内亿级位元传输率之无线基频传收机之高性能、低功率之关键软/硬矽智财
设计,如前端數位重取样IP,符号同步IP,通道预估IP,载波同步IP,FFT/
IFFT IP,LDPC 编解码IP,空间—时间解码IP 等…
3. 多核心及加速數器和平台设计及其在基频數位信号处理之运算。
4. 前瞻电子层级之合成设计与验证及系统评估。
5. SOC 整合设计与验证流程发展。
这些技术分在五个子计画与总计画执行,于三年中研发完成。第一年完成各功能方
块之基频讯号处理演算法之C (System C)与Matlab 设计及规格订定,并建立设计与系统
平台与验证环境,同时开始进行最上层之各功能方块IP 之C (System C)与Matlab 系统
整合设计。第二年除了完成第一版各关键IP 之FPGA 及ASIC 设计及验证,并利用多
核心平台环境完成评估与系统验证,并且我们会以第一年基频传收机之成果继续作更进
阶之系统规格发展与增进,藉以持续改进设计平台之效能。第三年除了改进前一年之IP
设计外将配合多核心平台和本计画研发的IPs,作系统雏型验证与展示。最后也将以所
设计之适用于无线高解析多媒体影音介面之室内亿级位元传输率之无线基频传收机之
各种规格尝试作多模式之雏型与展示。
The goal of this project is to develop core technologies and design platform for Wireless
Personal Area Network (WPAN) baseband transceiver. We will use the under developing
standard IEEE 802.15.3c for Multi-Gbps wireless personal area network (WPAN) as our
design platform. Furthermore, the system design and IP technologies will try to extend to
Wireless High Definition Multimedia Interface (WirelessHDMI) application. The objects are
to develop the following core technologies:
1. System design and performance evaluation of broadband transceiver receiver for
indoor 60GHz Multi-Gbps wireless baseband transceiver with extension to
WirelessHDMI application.
2. Low-power and high-performance ASIC soft/hard IP design for key function blocks
indoor 60GHz Multi-Gbps wireless baseband transceiver including front-end digital
resmapling IP, symbol synchronizer IP, channel estimator IP, carrier synchronizer IP,
FFT/IFFT IP, LDPC codec IP, space-time decoder IP, and etc..
3. Low-power and high-performance Multi-core platform and accelerator IP designs
for those aforementioned related baseband signal processing operations.
4. System evaluation and verification of baseband system by using Multi-core
platform.
5. Electronic System Level (ESL) synthesis and verification methodology for
communication IPs.
6. System integration, realizations and demonstrations.
All these core techniques will be developed by group project and five subprojects in
three years. In the first year, the algorithm of indoor 60GHz Multi-Gbps wireless baseband
transceiver will be coded in C (System C) and Matlab. The specifications evaluation of each
function will also be carried out. The system design flow and integrated methodology will be
setup to do system simulation. In the second year, the key modules and IPs will use FPGAs
and ASIC to verify their functionality and performance. Multi-core development environment
will be used to do the performance evaluation and verification. Also, more advanced
specifications will be investigated to improve the performance.
In the final year, we will improve the performance of the key IPs and will use Multi-core
platform with the developed IPs to do system prototyping and demonstration. Moreover,
Multi-mode possibility will be evaluated by combining different spec. of 802.15.3c or other
standards.
官方说明文件#: NSC97-2220-E009-037
URI: http://hdl.handle.net/11536/102557
https://www.grb.gov.tw/search/planDetail?id=1685677&docId=290539
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