次32奈米多重閘極元件的特性分析與模式建立---變異性與微縮性，高頻類比特性，以及介觀現象的探討

Abstract

在這個計畫中我們對次32 奈米多重閘極SOI CMOS 的元件特性作深入探討 及模型建立。在工作項目一中，我們將建立一個適用於不同buried oxide 厚度的 多重閘極SOI 元件的理論架構，我們的理論計算將涵蓋量子力學及原子等級的 效應。我們的模型可用來預測次32 奈米多重閘極SOI 元件的電性變異及其可微 縮性，將有助於多重閘極元件的設計。在工作項目二中，我們將綜合探討採用不 同製程模組的多重閘極SOI 元件的高頻及類比特性。本研究可用來初步評估多 重閘極SOI CMOS 技術在高頻及類比應用的發展潛力。在工作項目三中，我們 將探討極小尺寸多重閘極元件的介觀現象。本研究對於瞭解次32 奈米多重閘極 SOI 電晶體的載子傳輸特性十分重要。

In this project we conduct investigation and modeling for sub-32nm multiple-gate SOI CMOS. In task I, we will establish a theoretical framework for multi-gate SOI devices with various buried oxide thickness. We will further enhance our theoretical calculations by including quantum-mechanical and atomistic effects. Our model will be used to predict the variability and scalability of sub-32nm multi-gate SOI devices, and will be instrumental in multi-gate device design. In task II, we will conduct a comprehensive investigation of the RF/analog performance for multi-gate SOI devices fabricated by various process modules. Our investigation will be instrumental in early anticipation of the potentials of multi-gate SOI CMOS technology for RF/analog applications. In task III, we will investigate the mesoscopic phenomena in ultra-scaled multi-gate devices. Our investigation will be crucial to the understanding of carrier transport in sub-32nm multi-gate SOI MOSFETs.