高度微縮金氧半電晶體應變工程及物理機制之研究

Abstract

本計畫為期三年，針對應變矽技術重要議題進行研究，如應力量測、雜質擴散、 通道背向散射、表面缺陷密度、微觀物理、以及製程演進等。 第一年將進行下列項目 (針對佈局引致應力的n 型金氧半電晶體且特性尺度低至40 奈米左右): (1)量測閘極介 電層穿隧電流以反推通道內部應力。同一元件上的載子遷移率和臨界電壓將一併萃 取，也將萃取通道背向散射係數; (2)量測邊緣直接穿隧電流以得到特定應力下所造成的 橫向擴散; (3)使用低頻雜訊量測技術萃取出介面缺陷密度，也將提出並量化物理模式 ; (4)運作嶄新串聯電阻萃取方法，並檢驗串聯電阻所造成的影響;以及(5)進行計算電 洞能帶結構在不同應力大小及方位下的重要物理參數值。 第二年除繼續強化前一年 研究品質外，亦將進行下列項目(針對佈局引致應力的p 型金氧半電晶體且特性尺度 低至40 奈米左右): (1)量測閘極介電層穿隧電流以反推通道內部應力大小。同一元件 上的載子遷移率和臨界電壓將一併萃取，也將萃取通道背向散射係數; (2)量測邊緣直接 穿隧電流決定橫向擴散; (3)使用低頻雜訊量測技術萃取出介面缺陷密度，強化物理模 式;以及(4)進行金屬閘高K 介電層電晶體完整的應變下電性量測: 次臨界電流、閘極 電流、邊緣電流、基座電流、載子遷移率、臨界電壓、介電層與矽介面缺陷密度等， 並與物理模式作一關聯。 第三年除繼續強化前兩年研究品質外，亦將進行下列項目 (針對佈局技術製造應力電晶體且特性尺度可望至32 奈米以下): (1)量測其閘極介電 層電流反推通道內部應力大小。同一元件上的載子遷移率和臨界電壓將一併萃取，也 將萃取通道背向散射係數; (2)量測邊緣電流以得到特定應力下所造成的橫向擴散; (3) 使用低頻雜訊量測技術萃取出元件的介面缺陷密度;以及(4)繼續強化電性量測與金 屬閘高K 介電層電晶體物理模式的關聯，並建立通道內部應力之物理模式。 最終我 們將整合所有不同實驗條件下萃取的應力值嘗試提出一個三維應力物理模式。此模式 的驗證將與文獻數據作一比較，並嘗試納入介電層與矽介面的缺陷密度物理模式，機 械應力下雜質擴散物理模式，次臨界電流物理模式，閘極電流物理模式，邊緣電流物 理模式，基座電流物理模式，載子遷移率物理模式，臨界電壓物理模式等，以為應變 工程實際所用。

This is a three-year project dedicated to the strained silicon engineering in highly scaled MOSFETs concerning the stress measurement, dopant diffusion, channel backscattering, interface states, microscopic physics, and aggressively scaled process technologies. In the first year, the following items will be carried out (primarily on n-MOSFETs with the layout induced stress and with the feature size down to 40 nm or so): (1) measurement of channel stress via the gate tunneling current; also extracted are the carrier mobility and threshold voltage, as well as the channel backscattering coefficient, on the same devices; (2) measurement of dopant diffusion near the source/drain corner via edge direct tunneling; (3) measurement of interface states via the low-frequency noise, along with the quantified physical models; (4) with the novel series resistance extraction method, the effect of series resistance will be highlighted; and (5) calculation of the important physical parameters for the hole’s band structures under the stress magnitude and orientation. The goal of the second year is that we will further strengthen the quality of the works in the first year. Besides, we will explore the additional items (primarily on p-MOSFETs with the layout induced stress and feature size down to 40 nm or so): (1) measurement of channel stress via gate direct tunneling; also extracted on the same devices are the carrier mobility and threshold voltage, as well as the channel backscattering coefficient; (2) measurement of lateral diffusion via edge direct tunneling; (3) measurement of the interface states using the low-frequency noise along with the enhanced physical models; and (4) comprehensive electrical measurements for metal-gate/high-K strained MOSFETs, such as subthreshold current, gate current, edge current, substrate current, carrier mobility, threshold voltage, and interface states, along with a linkage to the underlying physical models. As to the third year, we will also enhance the quality of the works over the past two years. In addition, the following items will be conducted (primarily on the layout induced stress and with the feature size expected down to 32 nm and beyond): (1) measurement of channel stress via gate current; also extracted on the same devices are the carrier mobility and threshold voltage, as well as the channel backscattering coefficient; (2) measurement of lateral diffusion via edge current; (3) measurement of the interface states using the low-frequency noise along with the updated physical models; and (4) elaborating on the relation between electrical characteristics and physical mechanisms underlying the metal-gate/high-K strained MOSFETs. Eventually, we will integrate all experimentally determined stress values with the aim of constructing a 3-D stress physical model. The validity of the 3-D model will be compared with literature data while the followings will be incorporated as well: the interface states physical model, the stress induced dopant diffusion physical model, the subthreshold current physical model, the gate current physical model, the edge current physical model, the substrate current physical model, the carrier mobility physical model, the threshold voltage physical model, etc. The resulting integration tool can find practical applications in the areas of strain engineering.