金屬閘極/高介電係數材料互補式金氧半場效電晶體在45到22奈米世代之應用(I)

Abstract

發展金屬閘極/高介電質技術對45nm節點的CMOSFET而言是必須的，因為此技術可用來減少閘極漏電流，以減少直流功率消耗。Intel的共同創辦人，摩爾定律的發明者Golden Moore認為，金屬閘極/高介電質技術是過去四十年來電晶體最重要的發明，這項重要的發明相當可能得到諾貝爾獎。我們是高閘極介電質領域的先驅者之一，早在1998年就開始此領域上的研究，我們研究過的介電質如Al2O3、La(Al)O3、HfLaO(N)已被世界各地的研究者所引用，包括IBM及H. Iwai教授(IEEE Electron Devices前主席，Eber＇s獎的所有人)等。目前HfO-based的高介電質已被Intel用來作45nm節點電晶體的閘極介電質，其等效氧化層厚度(equivalent-oxide-thickness；EOT)只有1~1.2nm，若要進一步的將技術推進至32nm或22nm節點，需要將高介電質的EOT進一步的降至1nm以下。不幸的是，HfO2的導帶差(EC)較小，造成較高的漏電流，為了因應此問題，需使用鑭系的閘極介電質或HfLaON，因為HfLaON之EC(2.3eV)較HfO2(1.5eV)高，鑭系介電質的重要性可從SELETE和IMEC的研究以及他們在2007年12月於IEDM發表的論文中得到證實。金屬閘極/高介電質技術所遇到的挑戰還有高的臨限電壓(Vt)，這是因為介面反應和氧缺陷造成的Fermi level pinning，會使Vt升高。對PMOS而言要克服此一難關更為困難，因為只有Ir 和 Pt具備夠高的功函數(理想狀態要大於5.2eV)，然而，Pt很難用RIE蝕刻，而Ir在高介電質HfSiON上則很不穩定，我們之前曾發展出熱穩定性高、和CMOS製成相容、富含Ir的金屬矽化物。因此本計劃第一年的目標是發展雙金屬閘極/高CMOSFET，其中我們用高熱穩定性、富含Ir的金屬矽化物當p – MOSFET的閘極，用HfSi當n – MOSFET的閘極。其EOT約為1.1~1.2nm，以使得功函數跟目標值(4.1和5.2eV)的差距在0.2 eV以內；n – MOSFET和p – MOSFET的遷移率分別應大於200和80 cm2/Vs；在85 oC下給予持續1小時、10MV/cm的偏壓，其偏壓溫度不穩定性(Bias-Temperature Instability；BTI)須小於50mV，以得到好的可靠度。第二年和第三年的目標則希望進一步把等效氧化層厚度下降到0.7~1.0nm，且功函數和目標值的差値仍要在0.2 eV以內。我們使用HfLaO和覆蓋鑭系元素的HfSiON來達到如此薄的EOT，而且僅伴隨著少許Fermi-level pinning。這是目前所知唯一能達到目標的方法，目前有SELETE-Japan，IMEC，SNDL 以及我們曾使用過。這麼薄的EOT下，薄的base oxide和remote scaling會把遷移率降到100~150 cm2/Vs，然而即使在此情形下，將電路操作在85 oC，給予持續1小時10MV/cm的偏壓，仍能得到小於50mV的BTI。要達到上述的規格，必須作詳細的介面和氧空穴(vacancy)的分析，我們團隊中材料科學和介面特性的專家將負責此部份。此外，耶魯大學的T. P. Ma教授也會與我們合作並給我們建議以達成此目標。

Metal-gate/high-κ technology is required for 45 nm node and beyond CMOSFETs to reduce the intolerable high DC power dissipation from gate leakage current. According to Golden Moore- the Intel Co-Founder and Moore’s Law inventor, the Metal-gate/high-κ technology is the most important transistor innovation for past 40 years. This innovation is so important that is possible for Nobel Laureate. We are one of the early pioneers in leading high-κ gate dielectric research as early as 1998. Our developed high-κ Al2O3, La(Al)O3 and HfLaO(N) gate dielectrics gate dielectrics have been cited and followed worldwide, including IBM, Prof. H. Iwai (previous President, IEEE Electron Devices, Eber’s Award Owner) etc. Currently, the HfO-based high-κ dielectric has been used for Intel’s 45 nm node transistors with equivalent-oxide-thickness (EOT) of 1~1.2 nm. Further evolution of technology to 32 and 22 nm nodes require down-scaling the high-κ gate dielectric with EOT <1 nm. Unfortunately, the small conduction band offset (ΔEC) of HfO2 leads to a higher leakage current. To address this issue, the Lanthanide high-κ gate dielectric or mixed HfLaON is needed that is due to the inherent merit of higher ΔEC (2.3 eV) than that of HfO2 (1.5 eV). The importance of Lanthanide-based high-κ dielectric is evident from the followed works at SELETE and IMEC and their papers in International Electron Devices Meeting (IEDM), Dec. 2007. The other difficult challenge of metal-gate/high-κ technology is the higher threshold voltage (Vt) by Fermi-level pinning originated from interface reaction and oxygen defects. This is especially difficult for p-MOSFET since only Ir and Pt have the needed high work-function >target 5.2 eV in the Periodic Table. However, the Pt is difficult to etch by RIE and Ir is not stable even on high-κ HfSiON. We have previously invented the thermally stable and CMOS process-compatible Ir-rich silicide. Therefore, the first year goal of this project is to develop dual-metal-gates/high-κ CMOSFETs using the high temperature stable Ir-rich silicide and HfSi for respective p- and n-MOSFETs. The EOT is 1.1~1.2 nm with proper work-function within 0.2 eV to target 4.1 and 5.2 eV. The mobility for n- and p-MOSFETs should be >200 and >80 cm2/Vs. Good reliability of small Bias-Temperature Instability (BTI) less than 50 mV is also necessary of this technology under 10 MV/cm and 85oC stress condition for 1 hr. The 2nd and 3rd year goals of this project are to further scale the EOT to 0.7~1.0 nm with still good work-function within 0.2 eV of target 4.1 and 5.2 eV for n- and p-MOSFETs, respectively. Here we will study both the mixed HfLaO and Lanthanide-capped HfSiON to achieve this small EOT with less Fermi-level pinning. Such methods are the only known solutions to above goal, which has been used by SELETE-Japan, IMEC, SNDL and us. At such small EOT, the small base oxide and remote scaling will decrease the mobility to 100~150 cm2/Vs. However, good BTI reliability of <50 mV should still be obtained for circuit operation at 10 MV/cm and 85oC stress for 1 hr. To achieve these tight specifications shown above, detailed interface and oxygen vacancy analysis and understanding are inevitable. Our team experts in material science and interface characterization will be responsible to this part. Besides, Prof. T. P. Ma at Yale University will be our international advisor to achieve these aggressive goals.