奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫二：極低寄生電容之靜電放電防護技術以應用於超高速/超高頻積體電路

Abstract

追求更高的工作速度是射頻積體電路設計不斷努力的方向。在元件製程進入奈米領 域之後，射頻電晶體的操作頻率也得以順利地提昇。然而在奈米CMOS 製程中，靜電 放電（ESD）對射頻積體電路之可靠度的影響愈來愈嚴重，因此必須設計出適當的靜 電放電防護電路，以避免射頻積體電路遭受靜電放電轟擊而損壞。由於靜電放電防護 電路必須置於射頻積體電路之輸入與輸出接點，所以靜電放電防護電路的寄生電容必 須納入電路設計的考量中。 除了輸入與輸出接點的靜電放電防護電路必須經由特殊設計以降低寄生電容，另一 項重要的設計內容便是電源箝制靜電放電防護電路。搭配快速導通並擁有低箝制電壓 的電源箝制靜電放電防護電路，可縮小輸入點上的靜電放電防護元件尺寸。然而在奈 米製程中，電源箝制靜電放電防護電路中之靜電放電偵測電路有嚴重的漏電問題，所 以針對靜電放電偵測電路必須有創新的設計。 本計畫擬在 90-nm~45-nm 之奈米CMOS 技術中，建立靜電放電防護元件的高頻元 件模型，開發積體電路輸入輸出端靜電放電防護元件之標準單元，並搭配阻抗匹配電 路，以提供射頻及高速積體電路實際產品之應用。此外，本計畫擬開發超低漏電之靜 電放電偵測電路，以解決電源箝制靜電放電防護電路中靜電放電偵測電路的漏電問題。

It is the trend to improve the operation frequency of RF ICs. With the nanoscale CMOS processes, it is suitable to implement RF circuits with higher operation frequencies. However, the damage caused by electrostatic discharge (ESD) zapping is the major reliability issue in nanoscale CMOS processes. To protect the IC against ESD damages, on-chip ESD protection circuits must be included in the ICs. The ESD protection circuit must be provided at input/output (I/O) port for ESD protection, and the parasitic capacitance of ESD protection circuit must be taken into consideration in the design phase. Besides the ESD protection circuit at the I/O port, the power-rail ESD clamp circuit must be provided in ICs to achieve whole-chip ESD protection. With properly designed power-rail ESD clamp circuit, the dimensions of the ESD protection devices at I/O port can be minimized to mitigate their degradation on RF performances. However, the ESD detection circuit in the power-rail ESD clamp circuit introduces serious leakage current in nanoscale CMOS processes. Therefore, novel ESD detection circuit must be developed. In this project, the ESD protection circuit suitable for the ESD protection in RF ICs will be developed. The high frequency model of the ESD protection circuit will also be developed by using the measured result of the fabricated test chip. Finally, the cells of the ESD protection circuits will be established with their impedance matching network. Besides, the new ESD detection circuit for the power-rail ESD clamp circuit will be proposed to overcome the leakage current problem. The abovementioned designs will be studied in advanced CMOS processes, including 90-nm, 65-nm, and 45-nm CMOS processes.