系統層級之多核心嵌入式系統發展與驗證環境---子計畫四：多核心嵌入式系統效能與耗能分析監測與改善(I)

Abstract

近年來隨著嵌入式系統晶片功能越益強大，嵌入式系統晶片也漸漸朝向複雜之多核心設計以提升效能、降低耗能與成本。然而傳統多核心嵌入式系統晶片設計方法及工具多半針對已完成之系統晶片進行效能與耗能的評估，對於設計初期或設計的過程中所能得到的效能與耗能參數所知有限，也無法有效的在設計中期或初期，偵測出多核心嵌入式系統晶片可能遭遇的軟硬體效能與耗能問題，更無法有效透過軟體或硬體技術來改善。因此本子計畫的主要目的在於設計一套多核心嵌入式系統晶片之效能與耗能分析與監測的工具，以協助多核心嵌入式系統晶片與軟體設計者，在設計期間藉由工具的分析，事先掌握多核心嵌入式系統晶片硬體與軟體的效能與耗能特性，並進而在軟、硬體設計層面加以改進。本子計畫規劃以三年時間研究多核心嵌入式系統晶片之效能與耗能分析、監測與提升技術，計畫第一年透過實驗分析各種影響多核心嵌入式系統晶片硬體與軟體之效能與耗能參數，嘗試使用一個快速高階的效能與耗能模型加以評估各種多核心嵌入式系統晶片之軟硬體架構。建立在此一效能與耗能模型與分析工具之上，計畫第二年更進一步在設計之晶片系統上加入硬體與作業系統層次之效能與耗能監控元件來強化上述工具的設計，達到即時監測與調整的目的。計畫第三年則與硬體、作業系統、應用等子計畫合作開發多核心嵌入式系統晶片之高效能、低耗能技術，並透過前述工具加以分析、評估與驗證。

Multi-core embedded systems and system on chips (SoCs) which achieve a higher performance and a better cost- and energy-efficiency than single-core embedded systems become more and more popular recently. Unfortunately, conventional approaches for optimizing performance and energy consumption of multi-core SoCs rely on fine tuning after the hardware (H/W) and software (S/W) are completely developed. It is very difficult for system and software engineers to identify potential H/W and S/W performance and power consumption problems while the system is being developed. The problem makes multi-core SoCs very difficult to design and optimize. In this project, performance and power consumption profiling and monitoring tools for multi-core embedded systems and SoCs are proposed. The tools which provide the performance and power consumption monitoring and profiling of multi-core SoCs facilitate system and software designers to diagnose performance and power consumption problems and bottlenecks while the system is being developed. Based on these performance and power consumption analyses and results, system and software designers can further optimize multi-core embedded SoCs during design phase. In the first year, a high-level performance model and a power consumption model are proposed. The high-level models provide fast performance evaluation results and power consumption reports to designers. Based on the high-level models, hardware and system software components are added to the target multi-core embedded system and SoC to support real-time performance and power consumption monitoring. Based on the results collected in the first and second years, this subproject will work together with other subprojects to propose and evaluate high performance and low power designs for multi-core embedded SoCs.