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dc.contributor.author陸志豪en_US
dc.contributor.author廖彥欽en_US
dc.contributor.author李鎮宜en_US
dc.contributor.author張錫嘉en_US
dc.contributor.author許雅三en_US
dc.date.accessioned2014-12-16T06:12:57Z-
dc.date.available2014-12-16T06:12:57Z-
dc.date.issued2009-02-01en_US
dc.identifier.govdocH03M013/11zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/103920-
dc.description.abstract本發明係揭露一種應用於低密度對稱檢查碼(LDPC)解碼器之運算方法及其電路,其係將原有位元節點併入查核節點中同時進行運算,只需要利用原本查核節點的輸入訊息,產生新的位元節點訊息,查核節點再執行原本的運算時,也可以同時利用新的查核節點輸出訊息與原本查核節點之輸入訊息去更新位元節點的訊息,經由查核節點所得到的訊息,不僅執行原本查核節點的運算,也同時產生原本位元節點的輸出訊息。如此即可有效降低LDPC解碼器所需要的記憶體數量,並同時提高解碼速度。zh_TW
dc.language.isozh_TWen_US
dc.title應用於低密度對稱檢查碼（LDPC）解碼器之運算方法及其電路zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumber200906073zh_TW
Appears in Collections:Patents


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