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dc.contributor.authorChuang Ching-Teen_US
dc.contributor.authorChen Yin-Nienen_US
dc.contributor.authorHsieh Chien-Yuen_US
dc.contributor.authorFan Ming-Longen_US
dc.contributor.authorHu Pi-Hoen_US
dc.contributor.authorSu Pinen_US
dc.date.accessioned2014-12-16T06:13:52Z-
dc.date.available2014-12-16T06:13:52Z-
dc.date.issued2014-05-06en_US
dc.identifier.govdocG11C011/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104386-
dc.description.abstractThe present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.zh_TW
dc.language.isozh_TWen_US
dc.titleIndependently-controlled-gate SRAMzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08717807zh_TW
Appears in Collections:Patents


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