標題: Address generation apparatus and method for quadratic permutation polynomial interleaver
作者: Lee Shuenn-Gi
Wang Chung Hsuan
Sheen Wern-Ho
公開日期: 18-Jun-2013
摘要: An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus.
官方說明文件#: G11C029/00
G01R031/28
G06F011/00
G06F012/00
G06F013/00
G06F013/28
URI: http://hdl.handle.net/11536/104472
專利國: USA
專利號碼: 08468410
Appears in Collections:Patents


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