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dc.contributor.authorChiu Yi-Teen_US
dc.contributor.authorChang Ming-Hungen_US
dc.contributor.authorYang Hao-Ien_US
dc.contributor.authorHwang Weien_US
dc.date.accessioned2014-12-16T06:14:01Z-
dc.date.available2014-12-16T06:14:01Z-
dc.date.issued2013-05-07en_US
dc.identifier.govdocG11C011/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104481-
dc.description.abstractA static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.zh_TW
dc.language.isozh_TWen_US
dc.titleStatic random access memory cell and method of operating the samezh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08437178zh_TW
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