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dc.contributor.authorCHANG Yien_US
dc.contributor.authorLIN Yueh-Chinen_US
dc.contributor.authorWANG Huan-Chungen_US
dc.date.accessioned2014-12-16T06:14:43Z-
dc.date.available2014-12-16T06:14:43Z-
dc.date.issued2014-11-27en_US
dc.identifier.govdocH01L029/778zh_TW
dc.identifier.govdocH01L029/205zh_TW
dc.identifier.govdocH01L029/20zh_TW
dc.identifier.govdocH01L029/66zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104859-
dc.description.abstractAn enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure.zh_TW
dc.language.isozh_TWen_US
dc.titleEnhanced GaN Transistor and the Forming Method Thereofzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20140346523zh_TW
Appears in Collections:Patents


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