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dc.contributor.authorCHUANG Ching-Teen_US
dc.contributor.authorLIEN Nan-Chunen_US
dc.contributor.authorLIAO Wei-Nanen_US
dc.contributor.authorCHU Li-Weien_US
dc.contributor.authorCHANG Chi-Shinen_US
dc.contributor.authorTU Ming-Hsienen_US
dc.date.accessioned2014-12-16T06:14:50Z-
dc.date.available2014-12-16T06:14:50Z-
dc.date.issued2014-03-06en_US
dc.identifier.govdocG11C011/412zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104945-
dc.description.abstractA control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.zh_TW
dc.language.isozh_TWen_US
dc.titleCONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOFzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20140063918zh_TW
Appears in Collections:Patents


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