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dc.contributor.authorLi, Katherine Shu-Minen_US
dc.contributor.authorLee, Chung-Lenen_US
dc.contributor.authorSu, Chauchinen_US
dc.contributor.authorChen, Jwu E.en_US
dc.date.accessioned2014-12-08T15:13:35Z-
dc.date.available2014-12-08T15:13:35Z-
dc.date.issued2007-08-01en_US
dc.identifier.issn0923-8174en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s10836-007-0759-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/10495-
dc.description.abstractA novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.en_US
dc.language.isoen_USen_US
dc.subjectoscillation ring (OR) test schemeen_US
dc.subjectinterconnect testen_US
dc.subjectSOC testingen_US
dc.subjectstuck-at faultsen_US
dc.subjectopen faultsen_US
dc.subjectdelay faultsen_US
dc.subjectcrosstalk glitchesen_US
dc.subjectIEEE P1500en_US
dc.subjectwrapper cell designen_US
dc.titleIEEE standard 1500 compatible oscillation ring test methodology for interconnect delay and crosstalk detectionen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s10836-007-0759-5en_US
dc.identifier.journalJOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONSen_US
dc.citation.volume23en_US
dc.citation.issue4en_US
dc.citation.spage341en_US
dc.citation.epage355en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000248414800006-
dc.citation.woscount9-
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