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dc.contributor.authorJOU Shyh-Jyeen_US
dc.contributor.authorLin Jhih-Yuen_US
dc.contributor.authorChuang Ching-Teen_US
dc.contributor.authorTu Ming-Hsienen_US
dc.contributor.authorTsai Ming-Chienen_US
dc.date.accessioned2014-12-16T06:15:16Z-
dc.date.available2014-12-16T06:15:16Z-
dc.date.issued2012-03-08en_US
dc.identifier.govdocG11C011/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105205-
dc.description.abstractThe present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system.zh_TW
dc.language.isozh_TWen_US
dc.titleASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOFzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20120057399zh_TW
Appears in Collections:Patents


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