Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | JOU Shyh-Jye | en_US |
| dc.contributor.author | Lin Jhih-Yu | en_US |
| dc.contributor.author | Chuang Ching-Te | en_US |
| dc.contributor.author | Tu Ming-Hsien | en_US |
| dc.contributor.author | Tsai Ming-Chien | en_US |
| dc.date.accessioned | 2014-12-16T06:15:16Z | - |
| dc.date.available | 2014-12-16T06:15:16Z | - |
| dc.date.issued | 2012-03-08 | en_US |
| dc.identifier.govdoc | G11C011/00 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/105205 | - |
| dc.description.abstract | The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system. | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF | zh_TW |
| dc.type | Patents | en_US |
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20120057399 | zh_TW |
| Appears in Collections: | Patents | |
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