Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chuang Ching-Te | en_US |
dc.contributor.author | Yang Hao-I | en_US |
dc.contributor.author | Lin Jihi-Yu | en_US |
dc.contributor.author | Yang Shyh-Chyi | en_US |
dc.contributor.author | Tu Ming-Hsien | en_US |
dc.contributor.author | Hwang Wei | en_US |
dc.contributor.author | Jou Shyh-Jye | en_US |
dc.contributor.author | Lee Kun-Ti | en_US |
dc.contributor.author | Li Hung-Yu | en_US |
dc.date.accessioned | 2014-12-16T06:15:25Z | - |
dc.date.available | 2014-12-16T06:15:25Z | - |
dc.date.issued | 2011-06-02 | en_US |
dc.identifier.govdoc | G11C007/10 | zh_TW |
dc.identifier.govdoc | G11C007/00 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/105302 | - |
dc.description.abstract | A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20110128796 | zh_TW |
Appears in Collections: | Patents |
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