完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Lee, Chen-yi | en_US |
| dc.contributor.author | Chung, Ching-che | en_US |
| dc.date.accessioned | 2014-12-16T06:15:38Z | - |
| dc.date.available | 2014-12-16T06:15:38Z | - |
| dc.date.issued | 2010-04-15 | en_US |
| dc.identifier.govdoc | H03L007/099 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/105423 | - |
| dc.description.abstract | A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal. | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | Digital Loop Filter for All-Digital Phase-Locked Loop Design | zh_TW |
| dc.type | Patents | en_US |
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20100090769 | zh_TW |
| 顯示於類別: | 專利資料 | |

