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dc.contributor.authorChin, Alberten_US
dc.date.accessioned2014-12-16T06:15:44Z-
dc.date.available2014-12-16T06:15:44Z-
dc.date.issued2009-11-12en_US
dc.identifier.govdocH01L021/425zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105466-
dc.description.abstractThis invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability<32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.zh_TW
dc.language.isozh_TWen_US
dc.titleMethod for making very low Vt metal-gate/high-k CMOSFETs using self-aligned low temperature shallow junctionszh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20090280630zh_TW
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