完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chin, Albert | en_US |
dc.date.accessioned | 2014-12-16T06:15:44Z | - |
dc.date.available | 2014-12-16T06:15:44Z | - |
dc.date.issued | 2009-11-12 | en_US |
dc.identifier.govdoc | H01L021/425 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/105466 | - |
dc.description.abstract | This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability<32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Method for making very low Vt metal-gate/high-k CMOSFETs using self-aligned low temperature shallow junctions | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20090280630 | zh_TW |
顯示於類別: | 專利資料 |