Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

Abstract

We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.