Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

標題:	Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions
作者:	Cheng, C. F. Wu, C. H. Su, N. C. Wang, S. J. McAlister, S. P. Chin, Albert 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	2007
摘要:	We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
URI:	http://hdl.handle.net/11536/7168 http://dx.doi.org/10.1109/IEDM.2007.4418939
ISBN:	978-1-4244-1507-6
DOI:	10.1109/IEDM.2007.4418939
期刊:	2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2
起始頁:	333
結束頁:	336
顯示於類別：	會議論文

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