完整後設資料紀錄
DC 欄位語言
dc.contributor.authorWu, Jieh-Tsorngen_US
dc.contributor.authorLee, Zwei-Meien_US
dc.contributor.authorWang, Cheng-Yehen_US
dc.date.accessioned2014-12-16T06:15:56Z-
dc.date.available2014-12-16T06:15:56Z-
dc.date.issued2008-07-31en_US
dc.identifier.govdocG11C027/02zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105581-
dc.description.abstractA precharge sample-and-hold circuit is formed by coupling a buffer with an input port and making use of a switch to conduct the circuit between the buffer and a total load capacitor for precharging according the state of a sample-and-hold circuit. When the sample-and-hold circuit is in the sample mode, it precharges the total load capacitor. When the sample-and-hold circuit is in the hold mode, the influence to the sampled signal is further reduced due to the precharging. The requirements of swing rate, output voltage swing, gain-bandwidth product for the opamps can therefore be reduced, hence being applicable to the realization of the design of advanced fabrication technologies of low supply voltages.zh_TW
dc.language.isozh_TWen_US
dc.titlePre-charge sample-and-hold circuitzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20080180136zh_TW
顯示於類別:專利資料


文件中的檔案:

  1. 20080180136.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。