標題: | Clock switching circuit |
作者: | Wu, Jian-Hua Hwang, Wei |
公開日期: | 5-七月-2007 |
摘要: | The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs. |
官方說明文件#: | G06F001/08 |
URI: | http://hdl.handle.net/11536/105648 |
專利國: | USA |
專利號碼: | 20070152719 |
顯示於類別: | 專利資料 |