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dc.contributor.authorWang, Yu-Jenen_US
dc.contributor.authorCheng, Chao-Chungen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2014-12-08T15:14:10Z-
dc.date.available2014-12-08T15:14:10Z-
dc.date.issued2007-05-01en_US
dc.identifier.issn1051-8215en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSVT.2007.894050en_US
dc.identifier.urihttp://hdl.handle.net/11536/10854-
dc.description.abstractThis paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14% of searching time when compared with the previous design.en_US
dc.language.isoen_USen_US
dc.subjectH.2641AVCen_US
dc.subjectmotion estimationen_US
dc.subjectvideo codingen_US
dc.titleA fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video codingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSVT.2007.894050en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGYen_US
dc.citation.volume17en_US
dc.citation.issue5en_US
dc.citation.spage578en_US
dc.citation.epage583en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000246192100006-
dc.citation.woscount40-
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