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dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorSu, Chun-Jungen_US
dc.date.accessioned2014-12-08T15:14:31Z-
dc.date.available2014-12-08T15:14:31Z-
dc.date.issued2007-03-01en_US
dc.identifier.issn1536-125Xen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TNANO.2007.891828en_US
dc.identifier.urihttp://hdl.handle.net/11536/11043-
dc.description.abstractA novel field-effect transistor with Si nanowire (NW) channels is developed and characterized. To enhance the film crystallinity, metal-induced lateral crystallization (MILC) and/or rapid thermal annealing (RTA) techniques are adopted in the fabrication. In the implementation of MILC process, it is shown that the arrangement of seeding window plays an important role in affecting the resulting film structure. In this regard, asymmetric window arrangement, i.e., with the window locating on only one of the two channel sides is preferred. When MILC and RTA techniques are combined, it is found that single-crystal-like NWs are achieved, leading to significant performance improvement as compared with the control with channels made up of fine-grain structures by the conventional solid-phase, crystallized (SPC) approach. Field-effect mobility up to 550 cm(2)/V-s is recorded in this study.en_US
dc.language.isoen_USen_US
dc.subjectfield-effect transistoren_US
dc.subjectmetal-induced lateral crystallization (MILC)en_US
dc.subjectmobilityen_US
dc.subjectrapid thermal annealing (RTA)en_US
dc.subjectSi nanowireen_US
dc.titleHigh-performance poly-Si nanowire NMOS transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TNANO.2007.891828en_US
dc.identifier.journalIEEE TRANSACTIONS ON NANOTECHNOLOGYen_US
dc.citation.volume6en_US
dc.citation.issue2en_US
dc.citation.spage206en_US
dc.citation.epage212en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000245109100011-
dc.citation.woscount26-
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