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dc.contributor.authorLin, CHen_US
dc.contributor.authorChen, CMen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:02:26Z-
dc.date.available2014-12-08T15:02:26Z-
dc.date.issued1996-08-01en_US
dc.identifier.issn0098-3063en_US
dc.identifier.urihttp://dx.doi.org/10.1109/30.536150en_US
dc.identifier.urihttp://hdl.handle.net/11536/1120-
dc.description.abstractThe I/O power consumption in MPEG-2 decoder is significant because of the wide connection with large capacitances to the frame buffer. To reduce the power dissipation on the Memory Bus, the Gray code encoding scheme is proposed to increase the correlation of the image data transferred on the bus. The bit switching probability in the re-coded data will then decrease and in turn the bus power consumption will be reduced. Combined with the proposed bus arbitration and scheduling scheme proposed in this paper, 22% reduction of power dissipation may be achieved.en_US
dc.language.isoen_USen_US
dc.titleLow power design for MPEG-2 video decoderen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/30.536150en_US
dc.identifier.journalIEEE TRANSACTIONS ON CONSUMER ELECTRONICSen_US
dc.citation.volume42en_US
dc.citation.issue3en_US
dc.citation.spage513en_US
dc.citation.epage521en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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