標題: | A tableless approach for high-level power modeling using neural networks |
作者: | Hsu, Chih-Yang Hsieh, Wen-Tsan Liu, Chien-Nan Jimmy Jou, Jing-Yang 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | power macromodel;power estimation;neural network;low power design;RTL |
公開日期: | 1-一月-2007 |
摘要: | For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models have to increase their complexity in order to meet the accuracy requirement. In this paper, we propose a tableless power model for complex circuits that uses neural networks to learn the relationship between power dissipation and input/output signal statistics. The complexity of our neural power model has almost no relationship with circuit size and number of inputs and outputs such that this power model can be kept very small even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear characteristic of power distributions and the effects of both state-dependent leakage power and transition-dependent switching power. The experimental results have shown the accuracy and efficiency of our approach on benchmark circuits and one practical design for different test sequences with wide range of input distributions. |
URI: | http://hdl.handle.net/11536/11307 |
ISSN: | 1016-2364 |
期刊: | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Volume: | 23 |
Issue: | 1 |
起始頁: | 71 |
結束頁: | 90 |
顯示於類別: | 期刊論文 |