完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Po-Tsun | en_US |
dc.contributor.author | Huang, C. S. | en_US |
dc.contributor.author | Chen, C. W. | en_US |
dc.date.accessioned | 2014-12-08T15:15:07Z | - |
dc.date.available | 2014-12-08T15:15:07Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.issn | 1099-0062 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/11361 | - |
dc.identifier.uri | http://dx.doi.org/10.1149/1.2739214 | en_US |
dc.description.abstract | In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 mu m length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions. (c) 2007 The Electrochemical Society. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Enhanced planar poly-Si TFT EEPROM cell for system on panel applications | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/1.2739214 | en_US |
dc.identifier.journal | ELECTROCHEMICAL AND SOLID STATE LETTERS | en_US |
dc.citation.volume | 10 | en_US |
dc.citation.issue | 8 | en_US |
dc.citation.spage | J89 | en_US |
dc.citation.epage | J91 | en_US |
dc.contributor.department | 光電工程學系 | zh_TW |
dc.contributor.department | 顯示科技研究所 | zh_TW |
dc.contributor.department | Department of Photonics | en_US |
dc.contributor.department | Institute of Display | en_US |
dc.identifier.wosnumber | WOS:000247213200026 | - |
dc.citation.woscount | 5 | - |
顯示於類別: | 期刊論文 |