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dc.contributor.authorHung, Jui-Huien_US
dc.contributor.authorChen, Sau-Geeen_US
dc.date.accessioned2014-12-08T15:15:21Z-
dc.date.available2014-12-08T15:15:21Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1834-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/11523-
dc.description.abstractThis paper proposes a novel systematic optimization algorithm for comparison operations required by a check node unit (CNU) in LDPC decoding, given any input number N-in. The algorithm can automatically synthesize an optimized fast comparison operations that guarantees a shortest comparison delay time of [log(2) (N-in - 1)] T-cmp and a minimized total number of two-input comparators, where T-cmp is the delay time of a comparator. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. The designed CNU is favourable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.en_US
dc.language.isoen_USen_US
dc.subjectLDPC codeen_US
dc.subjectdecoderen_US
dc.subjectcomparatoren_US
dc.titleA systematic optimized comparison algorithm for fast LDPC decodingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, VOLS 1-3en_US
dc.citation.spage225en_US
dc.citation.epage229en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000256344200041-
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