標題: Passive reduced-order macro-modeling for linear time-delay interconnect systems
作者: Tseng, Wenliang
Liu, Chien-Nan Jimmy
Su, Chauchin
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: model-order reduction;passive macromodels;state-space time-delays systems;transmission lines
公開日期: 1-Nov-2006
摘要: This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.
URI: http://dx.doi.org/10.1093/ietele/e89-c.11.1713
http://hdl.handle.net/11536/11625
ISSN: 0916-8524
DOI: 10.1093/ietele/e89-c.11.1713
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E89C
Issue: 11
起始頁: 1713
結束頁: 1718
Appears in Collections:Articles