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dc.contributor.authorChen, Hsiao-Yunen_US
dc.contributor.authorLin, Chih-Hsienen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2014-12-08T15:15:56Z-
dc.date.available2014-12-08T15:15:56Z-
dc.date.issued2006-09-01en_US
dc.identifier.issn1057-7130en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSII.2006.879094en_US
dc.identifier.urihttp://hdl.handle.net/11536/11879-
dc.description.abstractThis investigation proposes a novel dc-balanced low-jitter transmission code, a 4-PAM symmetric code, for a 4-PAM signaling system. The 4-PAM symmetric code preserves all of the useful characteristics of the 8B/10B code such as dc-balanced serial data and guaranteed transitions in the symbol stream for clock recovery. Moreover, the proposed method decreases the jitter of the timing transition of the data in the receiver and consumes half of the data bandwidth, because it transmits in 4-PAM. The design results using the UMC 0.18-mu m process demonstrate that the new transmission code can decrease the jitter of the transition point by +/- 25% of the transition region. The operation speed of the encoder/decoder for the 4-PAM symmetric code is 819 MHz with 16-b inputs (13.1 Gb/s) and 704 MHz with 16-b outputs (11.3 Gb/s).en_US
dc.language.isoen_USen_US
dc.subjectlow jitteren_US
dc.subject4-PAMen_US
dc.subjecttransmission codeen_US
dc.subject8B/10B codeen_US
dc.titleDC-balance low-jitter transmission code for 4-PAM-signalingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSII.2006.879094en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSen_US
dc.citation.volume53en_US
dc.citation.issue9en_US
dc.citation.spage827en_US
dc.citation.epage831en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000241006200007-
dc.citation.woscount0-
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