Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices

Abstract

In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metaloxide-semiconductor field-effect transistor (MOSFET) with high-kappa gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-kappa offset spacer to further improve the on-state driving current I-on to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current I-off by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-kappa material as a spacer. This enhanced fringing electric field can markedly increase I-on/I-off current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.