A comprehensive study on the FIBL of nanoscale MOSFETs

標題:	A comprehensive study on the FIBL of nanoscale MOSFETs
作者:	Tsui, BY Chin, LF 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	fringing-induced barrier lowering (FIBL);high dielectric constant material;MOSFET;silicon-on-insulator (SOI);stack gate dielectric
公開日期:	1-十月-2004
摘要:	Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the I-off with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 run. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.
URI:	http://dx.doi.org/10.1109/TED.2004.835022 http://hdl.handle.net/11536/26353
ISSN:	0018-9383
DOI:	10.1109/TED.2004.835022
期刊:	IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume:	51
Issue:	10
起始頁:	1733
結束頁:	1735
顯示於類別：	期刊論文

文件中的檔案：

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。