A comprehensive study on the FIBL of nanoscale MOSFETs

doi:10.1109/TED.2004.835022

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tsui, BY	en_US
dc.contributor.author	Chin, LF	en_US
dc.date.accessioned	2014-12-08T15:38:30Z	-
dc.date.available	2014-12-08T15:38:30Z	-
dc.date.issued	2004-10-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TED.2004.835022	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26353	-
dc.description.abstract	Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the I-off with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 run. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.	en_US
dc.language.iso	en_US	en_US
dc.subject	fringing-induced barrier lowering (FIBL)	en_US
dc.subject	high dielectric constant material	en_US
dc.subject	MOSFET	en_US
dc.subject	silicon-on-insulator (SOI)	en_US
dc.subject	stack gate dielectric	en_US
dc.title	A comprehensive study on the FIBL of nanoscale MOSFETs	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TED.2004.835022	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	51	en_US
dc.citation.issue	10	en_US
dc.citation.spage	1733	en_US
dc.citation.epage	1735	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000224104700027	-
dc.citation.woscount	17	-
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