Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, YH | en_US |
dc.contributor.author | Lai, CS | en_US |
dc.contributor.author | Lee, CL | en_US |
dc.contributor.author | Lei, TF | en_US |
dc.contributor.author | Chao, TS | en_US |
dc.date.accessioned | 2014-12-08T15:02:33Z | - |
dc.date.available | 2014-12-08T15:02:33Z | - |
dc.date.issued | 1996-07-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/16.502428 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/1205 | - |
dc.description.abstract | NH3-nitridation to create nitrogen-rich layers in-between the stacked layers of the poly-Si gate for pMOS application is proposed and demonstrated. Due to the blocking of fluorine diffusion in the poly-Si gate by the nitrogen-rich layers, the amount of fluorine in the gate oxide, consequently, the fluorine enhancement on boron penetration is reduced. The negative effects of the NH3-nitridized oxide were not found in this work. Moreover, this nitridized stacked poly-Si gate improves significantly the electrical characteristics of the gate oxide as a result of the indirect and slight nitridation at the gate oxide. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Nitridization of the stacked poly-Si gate to suppress the boron penetration in pMOS | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/16.502428 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 43 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 1161 | en_US |
dc.citation.epage | 1165 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1996UU61900017 | - |
dc.citation.woscount | 5 | - |
Appears in Collections: | Articles |
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