完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTseng, SCen_US
dc.contributor.authorMeng, Cen_US
dc.contributor.authorChen, WYen_US
dc.date.accessioned2014-12-08T15:16:26Z-
dc.date.available2014-12-08T15:16:26Z-
dc.date.issued2006-06-01en_US
dc.identifier.issn0916-8524en_US
dc.identifier.urihttp://dx.doi.org/10.1093/ietele/e89-c.6.725en_US
dc.identifier.urihttp://hdl.handle.net/11536/12165-
dc.description.abstractFour 50% duty-cycle divide-by-3 prescalers-positively/negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers-are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-mu m SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7 V supply, the SSH prescaler operates from 500 MHz to 2 GHz as the SHH prescaler performs from 1 GHz to 3.4 GHz. The input sensitivity level of both structures is about -5 dBm, while the maximum output power is also about -5 dBm. The core current consumption is 4.538 mA and 4.258 mA for the SSH and SHH prescalers, respectively.en_US
dc.language.isoen_USen_US
dc.subjectprescaler divide-by-3en_US
dc.subject50% duty cycleen_US
dc.subjectSiGeBiCMOSen_US
dc.titleTrue 50% duty-cycle SSH and SHHSiGeBiCMOS divide-by-3 prescalersen_US
dc.typeArticleen_US
dc.identifier.doi10.1093/ietele/e89-c.6.725en_US
dc.identifier.journalIEICE TRANSACTIONS ON ELECTRONICSen_US
dc.citation.volumeE89Cen_US
dc.citation.issue6en_US
dc.citation.spage725en_US
dc.citation.epage731en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000238234000009-
dc.citation.woscount3-
顯示於類別:期刊論文