標題: Synchronous sampling and SNR-based gain control in DS/CDMA systems
作者: Lin, You-Hsien
Lo, Shih-Lin
Lai, Wei-Chi
Juan, Ta-Yang
Hsu, Terng-Yin
資訊工程學系
Department of Computer Science
關鍵字: timing recovery;synchronization;phase interpolator;multiphase
公開日期: 2007
摘要: Timing synchronization is an important component in a receiver designed to recover data form sampling digital waveform. A synchronous sampling recovery with dual correlator differential (DCD) based acquisition with effects of auto-gain controller (AGC) is proposed to achieve fast timing acquisition for direct sequence / code division multiple access (DS/CDMA) system over frequency-selective fading channel in this paper. It measures both received DCD difference power to determine the good sampling phase from an all-digital phase interpolator based multiphase generator. This solution can tolerate 50ppm system clock offset (SCO) under frequency-selective fading channel. Hence, we not only to determine the good sampling phase fast, but also to arrive stable variable gain amplifier (VGA) with AGC controller in DS/CDMA system approaches.
URI: http://hdl.handle.net/11536/12200
ISBN: 978-1-4244-0582-4
期刊: 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers
起始頁: 136
結束頁: 139
Appears in Collections:Conferences Paper