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dc.contributor.authorHuang, Po-Tsangen_US
dc.contributor.authorChang, Shu-Weien_US
dc.contributor.authorLiu, Wen-Yenen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:16:37Z-
dc.date.available2014-12-08T15:16:37Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0582-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/12268-
dc.identifier.urihttp://dx.doi.org/10.1109/CIS.2007.12en_US
dc.description.abstractNovel low power schemes for energy-efficient ternary content-addressable memory (TCAM) are presented in this paper. The butterfly match-line scheme is based on the pseudo-footless clock-data pre-charged architecture. It connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. For applications like IP-address forwarding in a network router, a new don't-care based power gating and don't-care based hierarchical (DCBH) search-line scheme are proposed. The search-line is divided into global search-line (GSL) and local search-line (LSL) which is controlled by don't-care state in DCBH search-line scheme. Therefore, the power consumption on search line is reduced without any search time overhead. Besides, the power saving of the standby power is achieved by power gating technique. The proposed 256 x 128bit TCAM has been implemented with TSMC 0.13um CMOS technology. It shows 0.55ns of match evaluation time on search operation with 0.29 fJ/bit/search of energy efficiency.en_US
dc.language.isoen_USen_US
dc.titleA 256x128 energy-efficient TCAM with novel low power schemesen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/CIS.2007.12en_US
dc.identifier.journal2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papersen_US
dc.citation.spage32en_US
dc.citation.epage35en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000247000000008-
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