A 6Gbps serial link transmitter with pre-emphasis

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chu, Chang-Min	en_US
dc.contributor.author	Chuang, Chih-Hua	en_US
dc.contributor.author	Lin, Chi-Hsien	en_US
dc.contributor.author	Jou, Shyh-Jye	en_US
dc.date.accessioned	2014-12-08T15:16:41Z	-
dc.date.available	2014-12-08T15:16:41Z	-
dc.date.issued	2007	en_US
dc.identifier.isbn	978-1-4244-0582-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/12301	-
dc.description.abstract	In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1 similar to 5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18um 1P6M 1.8V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68mW for 6Gbps case.	en_US
dc.language.iso	en_US	en_US
dc.title	A 6Gbps serial link transmitter with pre-emphasis	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers	en_US
dc.citation.spage	73	en_US
dc.citation.epage	74	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000247000000018	-
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