1Gbps 串列連結收發器

Abstract

隨著積體電路製程技術的進步，對於需要高頻寬和低延遲晶片之間資料傳輸也隨之增加。本論文描述一個高速串列式連結輸入輸出界面之設計。傳輸資料頻率定於1Gbps。 傳送器使用一個鎖相迴路作為一個時脈電路來提供八個相位給八對一多工器。此鎖相迴路輸入頻率為31.25MHz，而輸出頻率為125MHz。平行資料的預先調整相位機制被使用來減少多工器的時脈限制。在多工器和資料驅動器之間的預先驅動器使用主動電感負載來增加頻寬。開汲極電流模式輸出驅動器使用預先加強電路來增加傳送資料位元轉變時期所需的電流源。接收器使用具有磁滯現象的比較器將傳送過來的資料放大成數位訊號。然後，一個操作在輸入資料頻率一半的時脈資料回復電路使用雙追蹤路徑控制機制來達到更好的時脈雜訊表現。最後，解多工器將時脈資料回復電路的輸出轉變成八個平行資料通道。 此傳送器採用0.35μm 2P4M CMOS製程技術實現。當鎖相迴路輸出時脈為125MHz時，量測結果顯示輸出時脈的方均根抖動和峰值抖動分別為11.42ps和82ps。傳送器能正常傳送出1Gbps的串列資料。在電壓電源為3.3V時，總消耗功率為141mW。

As the IC fabrication technology advances, the need for high-bandwidth and low-latency inter-chip data transfer has also increased. This thesis describes the design of a high-speed serial link I/O interface. The transmission data rate is targeted at 1Gbps. The transmitter uses a phase-locked loop (PLL) as a timing circuit to provide eight phases for the 8-to-1 multiplexer. The input frequency of the PLL is 31.25MHz and the output frequency is 125MHz. The pre-skew mechanism of the parallel data is used to reduce the timing constrain of the multiplexer. The pre-driver inserted between the multiplexer and the data driver uses active inductive peaking load to enhance the bandwidth. The open-drain current mode data driver uses a pre-emphasis circuit to increase the current during the data transition. The receiver uses the comparator with hysteresis to amplify the incoming data to full swing. Then, the clock and data recovery (CDR) operates at half of the input data rate and uses a dual-tracking path control mechanism to achieve better jitter performance. Finally, the de-multiplexer converts the CDR outputs to eight parallel data channels. The transmitter is fabricated in a TSMC 0.35μm 2P4M process. The measured RMS and peak-to-peak jitter of the 125MHz output clock of the PLL are 11.42ps and 82ps, respectively. The transmitter transmits 1Gbps serial data normally. Total power consumption is 141mW at 3.3V supply voltage.